#TSMC #Outlines #3nm #Roadmap #FinFlex #Nodes

As pathfinding, research, and development cycle for all-new manufacturing technologies stretches, foundries have to introduce revamped versions of their nodes in a bid to meet client requirements. TSMC on Thursday formally unveiled its N3 (3nm class) family of fabrication processes that will be used to build leading-edge chips in the next three years. One of the key features of N3 is FinFlex technology that gives chip designers additional ways to optimize performance, power, and die size.

Five 3nm Nodes

TSMC’s N3 family of process technologies will consist of five nodes in total, all of which will support FinFlex. The lineup includes the original N3, set to enter high-volume manufacturing (HVM) later this year, with the first chips set to be delivered in 2023; N3E with performance-per-watt and process window improvements; N3P with additional performance enhancements; N3S with increased transistor density, and N3X with support for increased voltages, enhanced power deliver; and augmented clock rate potential for ultra-high-performance applications. 

(Image credit: TSMC)

Just like TSMC announced, it will start making chips on its original N3 node later this year. This process technology is largely designed for early adopters from mobile and high-performance computing (read ASICs, CPUs, GPUs, etc.) industries that develop expensive chips (or chips for expensive devices), benefit from all kinds of performance, power, and area (PPA) improvements, and are willing to pay for them. 

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